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preliminary datasheet R1EX25512ASA00A r1ex25512ata00a serial p e ripheral interfac e 512k e eprom (64-kword 8-bit) r10 d s0 046e j02 0 0 rev.2.00 oct.04, 201 0 description r1ex25xxx se ries is the seria l pe ripheral interface c o m p atible (spi) e e prom (electric a lly erasable a n d pro g rammab l e rom). th ey realize h i g h sp eed , l o w power co nsu m p tio n an d a h i gh lev e l of reliab ility by e m p l o y in g adva nce d m o no s m e m o ry t echn o l o gy a n d c m os pr ocess an d l o w v o l t a ge ci rc ui t r y t echn o l o gy . t h ey al so ha ve a 12 8 - by t e page pr o g ram m i ng f unct i o n t o m a ke t h ei r wri t e op erat i o n fast er . note: renesas electronics' seri a l ee p r o m s ar e au tho r iz ed for us in g c o n s u m er applications s u ch as cellular phones , cam c orde rs a n d a udi o e qui p m ent s . t h ere f ore , pl ease co n t act r e nesas el ect ro ni cs' sal e s o ffi ce bef o re u s i n g industrial applications s u c h as autom o tive sy st em s, em bedd ed c ont rol l e rs and m e t e rs. features ? si ngl e su p p l y : 1. 8 v t o 5. 5 v ? serial peri phe ral interface c o m p atible (spi bus) ? spi m o d e 0 (0 ,0 ), 3 (1 ,1) ? c l ock fre q u enc y : 5 m h z ( 2 . 5 v t o 5. 5 v) , 3 m h z ( 1 . 8 v t o 5. 5 v) ? po wer di ssi pat i on: ? stan db y: 5 a (m ax) ? active (read ): 5 m a (m ax) ? active ( write): 5 m a (m ax) ? a u t o m a t i c p a ge wr ite: 12 8- byte/p a g e ? write cycle time: 5 m s ( m a x ) ? endurance: 1,000k cycles @25 c ? data reten tio n : 100 years @2 5 c ? sm a ll size p ack ag es: sop-8p in , tssop-8 p in ? shipping ta pe and reel ? tsso p-8p in : 3 , 00 0 i c /r eel ? sop - 8pi n : 2 , 5 0 0 ic / r eel ? tem p erature ra nge: ? 40 to + 85 c ? lead f r e e pr odu ct. r10ds 0 0 46ej 020 0 rev.2.00 page 1 of 2 0 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a ordering information ty pe no. inte rna l orga n i za tion ope r a t ing v o lta g e f re que nc y pa c k a g e 5 mhz (2.5 v to 5.5 v) r1e x 2 551 2as a 00a 512k b i t (6553 6 8-pin sop/tssop (t op view) 1 2 3 4 8 7 6 5 v cc hold c d s q w v ss pin description pin na me func tio n c s e r i a l c l o c k d serial data input q serial d a ta out put s chip se lect w w r ite protect hold hold v cc s u p p l y v o ltag e v ss g r o u n d r10ds 0 0 46ej 020 0 rev.2.00 page 2 of 2 0 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a block diagram high voltage generator memory array y -select & sense amp. serial-parallel converter address generator control logic y decoder x decoder v cc v ss s w c hold d q absolute maximum ratings para mete r s y m b o l v a l u e u n i t supp l y v o ltag e relative to v ss v cc ? 0.6 to +7.0 v input voltag e relative to v ss v in ? 0.3 to v cc +0.3 v operatin g temperatur e rang e * 1 t o p r ? 40 to + 85 c storage temp e r ature ran ge t s tg ? 55 to + 125 c notes: 1. includi ng e l ectr ical c har acteris t ics and data r e tentio n. dc operating conditions pa rame t e r s y m b o l m i n ty p ma x u n i t v cc 1 . 8 5 . 5 v supp l y v o ltag e v ss 0 0 0 v v ih v cc 0.7 v cc + 0.3 v input voltag e v il ? 0.3 v cc 0.3 v operatin g temperat ur e rang e t opr ? 40 + 85 c capacitan ce (ta = + 2 5 c, f = 1 mhz) pa rame t e r s y mbol m i n ty p ma x u n i t te s t c onditi o n s input capac itan ce (d,c, s , w , h old ) c i n * 1 6.0 pf vin = 0 v output capacit ance (q) c i/o * 1 8.0 pf vout = 0 v note: 1. not 100 % tested. r10ds 0 0 46ej 020 0 rev.2.00 page 3 of 2 0 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a memor y cell characteristics (v cc = 1. 8 v t o 5. 5 v) t a =2 5 c t a =8 5 c n o t e s endur ance 1,000k c y c l es min. 100k c y cl es mi n. 1 data retenti on 100 ye ars min. 10 years mi n. 1 notes: 1. not 100 % tested data at shipment ? ? dc characteristics pa rame t e r s y m b o l m i n ma x u n i t te s t c onditi o n s input leak ag e current i li ? 2 a v cc = 5.5 v, v in = 0 to 5.5 v ( s , d, c, hol d , w ) output leaka g e current i lo ? 2 a v cc = 5.5 v, v out = 0 to 5.5 v (q) standb y i sb ? 5 a v in = v ss or v cc , s = v cc v cc = 5.5 v ? 3 m a v cc = 3.3 v, r ead at 5 mhz v in = v cc 0.1 / v cc 0.9 q = open i cc1 ? 5 m a v cc = 5.5 v, r ead at 5 mhz v in = v cc 0.1 / v cc 0.9 q = open ? 3 m a v cc = 3.3 v, write at 5 mhz v in = v cc 0.1 / v cc 0.9 v cc current active i cc2 ? 5 m a v cc = 5.5 v, write at 5 mhz v in = v cc 0.1 / v cc 0.9 v ol1 ? 0 . 4 v v cc = 2.5 to 5.5 v, i ol = 2 ma v ol2 ? 0 . 4 v v cc = 1.8 to 2.5 v, i ol = 1.5 ma v oh1 v cc 0.8 ? v v cc = 2.5 to 5.5 v, i oh = ? 2 ma output voltage v oh2 v cc 0.8 ? v v cc = 1.8 to 2.5 v, i oh = ? 0.4 ma r10ds 0 0 46ej 020 0 rev.2.00 page 4 of 2 0 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a ac characteristics test conditions ? ? ? ? ? ? ? + ? + para mete r s y m b o l a l t min m a x un i t no t e s clock freq uenc y f c f sc k ? s active setup time t slc h t c ss1 9 0 ? s not active se tup time t s hch t c ss2 9 0 ? s desel ect time t sh sl t cs 9 0 ? s active hol d time t chs h t cs h 9 0 ? s not active hold time t chs l ? ? ? ? ? ? ? ? hold not active t hhch ? ? hold active t hl ch ? ? hold active t chhl ? ? hold not active t chhh ? ? ? ? ? ? ? hold hig h to output lo w - z t hhqx t lz ? hold lo w to output lo w - z t hl qz t hz ? ? + %
r1ex25 512 asa00 a /r1ex2551 2ata00 a (ta = ? 40 t o + 85 c, v cc = 1. 8 v t o 5 . 5 v ) para mete r s y m b o l a l t min m a x un i t no t e s clock freq uenc y f c f sc k ? s active setup time t slc h t c ss1 1 0 0 ? s not active se tup time t s hch t c ss2 1 0 0 ? s desel ect time t sh sl t cs 2 5 0 ? s active hol d time t chs h t cs h 1 0 0 ? s not active hold time t chs l ? ? ? ? ? ? ? ? hold not active t hhch ? ? hold active t hl ch ? ? hold active t chhl ? ? hold not active t chhh ? ? ? ? ? ? ? hold hig h to output lo w - z t hhqx t lz ? hold lo w to output lo w - z t hl qz t hz ? ? + %
r1ex25 512 asa00 a /r1ex2551 2ata00 a timing wa veforms serial input timing s c t chsl t slch t chdx t clch t chcl t shch t chsh t shsl t dvch msb in lsb in d q high impedance hold timing t chhl s hold c d q t hlch t chhh t hlqz t hhqx t hhch outpu t timing s c d q lsb out addr lsb in t qlqh t qhql t shqz t ch t cl t clqv t clqx t clqv t clqx r10ds 0 0 46ej 020 0 rev.2.00 page 7 of 2 0 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a pin function serial d a t a ou tpu t (q) thi s out put si g n al i s used t o t r ansfe r dat a se ri al l y out o f t h e d e v i ce. data is sh i f ted ou t on th e fallin g edge of serial cl ock (c ) . serial d a ta in put (d) this input signal is use d to tra n sfe r data se rially into the device. it receives instructions, a d dresses , a n d the data to b e written . valu es are latch e d o n th e rising ed g e of serial clo c k (c). serial clock (c) th is inpu t signal p r ov id es t h e ti min g o f th e serial in terface. i n st r u ct i ons , a d d r esses , or da t a prese n t at se ri al dat a i n p u t ( d ) are l a t c hed o n t h e ri s i ng e d ge of ser i al cl ock (c ). dat a o n seri al dat a o u t p ut (q ) cha nge s aft e r t h e fal l i ng edge o f se ri al c l ock (c ) . chip select ( s ) w h en t h is input sig n a l is h i gh , th e d e v i ce is deselected and ser i al d a ta o u t pu t (q ) is at h i gh im p e d a n ce. u n less an in tern al write cycle is in progress, th e d e v i ce will b e in th e stan db y m o d e . dri v ing ch ip select ( s ) l o w en ab les th e d e v i ce, p l acing it in th e activ e po wer m o d e . after power-up , a falling ed ge on ch ip select ( s ) is requ ired p r i o r t o th e start of an y in stru ction . hold ( hold ) the hold ( hold ) signal is used t o pause any serial communications with th e d e v i ce with ou t d e selecting th e d e v i ce. during t h e h o l d co nd itio n, the serial d a ta outp u t (q) is h i gh i m p e d a n c e, and serial d a ta in p u t (d) and serial clo c k (c) are d o n ? t care. to start th e hold cond itio n , the de vice m u st be selected, with chi p select ( s ) dri v en lo w. write pr otec t ( w ) the m a in purpose of this i n put signal is t o freeze the size of the a r ea of m e m o ry that is protected a g ainst write i n st ruct i o ns (as speci fi e d by t h e val u e s i n t h e b p 1 a n d b p 0 b i t s of t h e st at us re gi st er). t h i s pi n m u st be dr i v en ei t h e r hi g h or l o w, a n d m u st be st a b l e d u ri ng al l wri t e ope rat i o ns. r10ds 0 0 46ej 020 0 rev.2.00 page 8 of 2 0 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a functional description statu s re gis t er th e f o llow i ng f i gu r e show s t h e status re gi st er f o rm at . the st at u s r e gi st er co nt ai ns a num ber of st at us a n d c ont r o l bi t s t h at ca n be rea d or set (as ap propriate) by speci fic i n structions. statu s re gis t er forma t srwd 0 0 0 bp1 bp0 wel wip b7 status register write disable block protect bits write enable latch bits write in progress bits b0 wip b it: th e write in prog ress (wip) b it i n d i cates wh ether th e m e m o ry is bu sy with a write o r write statu s reg i ster cycle. wel b it: th e write en ab le latch (wel) bit in d i cates th e statu s of t h e in t e rn al write enab le latch. bp1 , bp0 b its: th e blo c k pro t ect (bp1 , b p 0 ) b its are n o n - v o l atile. th ey d e fi n e th e size o f th e area to be software pr ot ect ed a g ai n s t w r i t e i n st ru ct i ons. b p 1, b p 0 a r e ? 0 ? st a t us at s h i p m e nt . sr wd b it: the statu s reg i ster write disable (sr w d) b it is op erated in co nju n c tion with th e write pro t ect ( w ) si gnal . the status re gister write dis a bl e ( s r w d) bi t an d wri t e pr ot ect ( w ) signal allo w th e d e v i ce to b e pu t in th e hard ware pro t ected m o de. in th is m o de, th e no n-v o l atile b its o f t h e statu s reg i ster (sr w d, bp1 , bp0) b eco m e read-on l y b its. sr wd is ? 0 ? status at shi p ment. instructions each i n struction starts with a single-byte code, as s u mm ariz ed in th e fo llowing tab l e. if an inv a lid i n stru ctio n is sen t (on e no t con t ain e d in t h e fo llowing tab l e) , t h e de vice aut o matically deselects itself. instruction set ins t ruc t i o n d e s c r i p t i o n ins t ruc t i o n fo rma t w r en w r ite enabl e 000 0 011 0 w rdi w r ite disabl e 000 0 010 0 rdsr read status r egister 000 0 010 1 w r sr w r ite status register 000 0 000 1 read read from me mor y arra y 000 0 001 1 w r it e w r ite to memor y arra y 000 0 001 0 r10ds 0 0 46ej 020 0 rev.2.00 page 9 of 2 0 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a write ena b le (w ren ): th e write en ab le latch (wel) b it m u st b e set p r i o r to each write and wrsr instru ct io n . th e on ly way to do th is is to sen d a write en ab le in st ru ctio n to th e d e v i ce. as sho w n i n th e fo llowing figu re, to sen d th is in st ru ction to th e d e v i ce, chip select ( s ) is d r i v en low, an d th e b its o f th e in stru ction b y te ar e s h i f t e d i n , on seri al dat a i n put ( d ). the de vi ce t h e n en ters a wait st ate. it waits for th e d e vice to be deselected, by chi p select ( s ) bei n g dri v e n hi g h . write ena b le (wren) seq u ence s w c d q instruction 01 2 3 4 5 6 high-z v ih v il v ih v il v ih v il v ih v il 7 r10ds 0 0 46ej 020 0 rev.2.00 page 1 0 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a write disabl e (w r d i): on e way of resettin g th e writ e en ab le latch (wel) b it is t o se n d a wri t e di sabl e i n st r u c t i on t o t h e de vi ce. as s h ow n in th e fo llo wi ng figu re, to send th is in stru ctio n to t h e d e v i ce, ch i p select ( s ) is driv en low, and th e b its o f th e i n stru ctio n b y te are sh ifted in, o n serial d a ta inp u t (d). th e d e v i ce th en en ters a wait state. it waits fo r the de vice to be deselected, by c h ip select ( s ) bei n g dri v en hi g h . t h e write en ab le latch (wel) bit, in fact, b e co mes reset b y an y of t h e fo llowing ev en ts: ? power-up ? wr d i i n st ruct i on e x ec ut i on ? wrsr instru ct io n co m p letio n ? write in stru ctio n co m p letio n write disabl e (wrdi) se quenc e s w c d q instruction 1 0 2 3 4 567 high-z v ih v il v ih v il v ih v il v ih v il r10ds 0 0 46ej 020 0 rev.2.00 page 1 1 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a rea d stat us regis t er ( r d s r) : th e read stat u s reg i ster (rdsr) in stru ctio n allo ws th e statu s register t o be read. t h e stat us re gister m a y be read at an y ti m e , ev en wh ile a write o r write statu s register cycle is in progres s . when on e of t h ese cycles is i n progress , it is recom m ended t o chec k t h e w r i t e in p r o g re ss ( wip ) bi t be fo re se ndi ng a ne w i n st ruct i o n t o t h e de vi ce. i t i s al so p o ssib l e to r e ad th e statu s reg i ster co n tinuou sly, as show n in th e fo llo w i ng f i gu r e . rea d status regis t er (rdsr) sequ en ce s w c d q status register out 01 2 3 4 5 6 7 0 1 2 3 4 5 6 77 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il th e status an d co n t r o l b its of t h e status regi ster are as follows: wip b it: th e write in prog ress (wip) b it i n d i cates wh ether th e m e m o ry is bu sy with a write o r write statu s reg i ster cycle. when s e t to 1, s u c h a cycl e is in progress. wh en reset to 0, no s u ch cycles are in progre ss. wel b it: th e write en ab le latch (wel) bit in d i cates th e statu s of t h e in t e rn al write enab le latch. wh en set to 1, the in tern al write en ab le latch i s set. when set to 0, th e in te rn al write en able latch is reset an d no write o r write statu s register inst ructions a r e acce pted. bp1 , bp0 b its: th e blo c k pro t ect (bp1 , b p 0 ) b its are n o n - v o l atile. th ey d e fi n e th e size o f th e area to be software p r o t ected ag ainst w r ite instructio n s . th ese b its are written w ith t h e write statu s reg i ster (wrsr ) in st ru ctio n. when one o r b o t h of t h e b l oc k p r ot ect (b p1 , b p 0) bi t s are set t o 1, t h e rel e va nt m e m o ry area ( a s de fi ne d i n t h e wri t e pr ot ect block size tabl e) becom e s protected agai n s t wri t e ( w r i te ) i n st ruct i o ns. the b l oc k pr ot ect (b p1 , b p 0) bi t s ca n be written p r ov id ed th at t h e hardware pro t ected m o d e h a s no t b een set. sr wd b it: the statu s reg i ster write disable (sr w d) b it is op erated in co nju n c tion with th e write pro t ect ( w ) si gnal . the status re gister write dis a bl e ( s r w d) bi t an d wri t e pr ot ect ( w ) signal allo ws t h e dev i ce to b e pu t in th e hardware pr ot ect ed m o d e ( w he n t h e st at us r e gi st er wri t e di sabl e (sr w d ) bi t i s set t o 1, a n d wr i t e pr ot ect ( w ) sig n a l is driv en lo w). in th is mo d e , th e non -vo l atile b its o f th e status reg i ster (sr w d, b p 1 , bp0 ) b e come read -on l y bits an d th e wri te status register (w r s r) i n struction is no longe r acce pted for exec ution. r10ds 0 0 46ej 020 0 rev.2.00 page 1 2 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a write statu s regis t er (wrsr): th e write stat u s reg i ster (wrsr) in st ru cti o n allo ws n e w v a lu es to b e written to th e statu s reg i ster. b e fore it can b e accepted, a write enable (wren) instruction m u st pre v iously ha ve bee n exec uted. aft e r the write enable (wre n) instruction has been dec o ded and exec uted, t h e device sets th e write en ab l e latch (wel). th e i n stru ctio n seq u e n ce is sh ow n i n t h e f o l l o wi ng fi gu r e . t h e wri t e s t at us r e gi st er ( w r s r ) i n st r u c t i on has n o ef f ect on b 6 , b 5 , b4 , b1 an d b 0 of t h e st at us r e gi st er. b 6 , b 5 a n d b4 ar e alway s rea d as 0. c h ip select ( s ) m u st be dri v e n h i gh a f t e r t h e ri si ng e d ge of seri al cl ock (c ) t h at l a t c hes i n t h e ei g h t h bi t of t h e dat a by t e , an d be fo re t h e next ri si n g e dge o f se ri al cl ock (c ). oth e rwise, th e write statu s r e g i ster (w rsr ) in st ru c t i o n i s not e x ec ut ed. as s o on as c h i p sel ect ( s ) i s dri v en hi gh , t h e self-tim ed write statu s reg i st er cycle (whos e duration is t w ) is in itiated . wh ile th e write statu s reg i ster cycle is in pr o g ress , t h e s t at us r e gi st er m a y st i l l be rea d t o chec k t h e value o f the write in p r o g re ss ( wip ) bit. t h e write in pr og ress ( wip ) bit is 1 d u ri n g the self -tim ed write status regi ster cycle, and is 0 when it is com p leted. whe n the cycle is co m p leted , write en ab le latch (wel) i s reset. th e write status re gister (w r s r) i n struction allows t h e user to chan ge t h e val u es of t h e b l oc k p r ot ect (b p 1 , b p 0 ) bi t s , t o d e fi ne t h e size of the area t h at is to be treate d as rea d -only, a s defi ned i n t h e st at us r e gi st er fo rm at t a bl e. the write stat us re gister (wrsr) inst ru cti o n also allows the user t o set or reset t h e sta t us register write disable (sr w d) bit in accorda n ce w ith the write prot ect ( w ) si gnal . t h e st at us r e gi st er wri t e di sabl e ( s r w d) bi t an d wri t e pr ot ect ( w ) si g n al al l o w s t h e devi ce t o be pu t i n t h e ha rd w a re p r ot ect ed m ode ( h pm ) . the wri t e st at us r e gi st er (w rsr ) instructio n is no t ex ecu t ed on ce th e hardware pro t ected mod e (hpm) is en tered . the c o ntents of the status re gister write di sabl e ( s r w d) and b l oc k p r ot ect (b p1 , b p 0) bi t s are f r oze n at t h ei r c u r r e n t v a lu es ju st b e fo re th e start of th e ex ecu tion of th e write st at us r e gi st er ( w r s r ) i n st ruct i o n . the ne w, up dat e d val u es take effect at the m o m e nt of com p letion of t h e e x ecu tion of write statu s reg i ster (wrsr) in stru ction . write statu s regis t er (wrsr) seque nce s w c d q status register in msb 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il r10ds 0 0 46ej 020 0 rev.2.00 page 1 3 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a rea d from m e m o ry array (rea d ): as sho w n i n the fo llo wi n g figu re, to send t h is in stru ction to th e d e v i ce, ch i p select ( s ) is first driv en low. th e b its of th e in stru ction b y te and th e add r ess b y tes are th en sh ifted in, on se rial data i n p u t (d ). t h e addresses are loade d i n to a n internal a d dres s re gister, a n d t h e byte of data at that address is sh i f ted ou t, o n serial d a ta ou tpu t (q). if c h ip select ( s ) con tin u e s to b e driv en low, th e in tern al add r ess re gister i s aut o m a tically incr em ented, a n d the byte of d a ta at th e n e w add r ess is sh ifted ou t. whe n t h e highest address is reached, the addres s c o unter rolls over to ze ro, allo wing t h e read cycle to be c ontinue d i nde fi ni t e l y . t h e wh ol e m e m o ry ca n, t h ere f ore , be rea d wi t h a si ngl e r e ad i n st r u ct i o n . the rea d cycle is term inated by drivi n g chi p select ( s ) high. t h e rising e d ge of the c h ip s e lect ( s ) signal can occ u r at any tim e during the cycle. t h e a d dresse d first byte ca n be any byte within a n y pa ge. t h e instruction i s not acce pted, an d is n o t ex ecu t ed , if a write cycle is curre n tly in progress . rea d from m e mor y arra y (read) seq u ence s w c d q 16-bit address data out 2 data out 1 01 2 3 4 5 6 7 0 1 2 3 13 14 15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 0 1 2 3 4 5 6 77 instruction no te: 1 . th e m e m o ry size is shown in th e fo llowing t a b l e. addr ess ra nge bits de v i c e r 1 e x 2 551 2 a address b i ts a15 to a0 r10ds 0 0 46ej 020 0 rev.2.00 page 1 4 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a write to me m o ry array ( w rite ): as sho w n i n the fo llo wi n g figu res, to sen d this in stru ctio n to th e d e v i ce, ch ip select ( s ) i s first driv en low. th e b its of the instruction byte, address byte, and at leas t one data b y te are th en sh ifted in, o n serial d a ta inp u t (d). th e i n stru ctio n is term in ated b y driv i n g ch i p select ( s ) h i gh at a b y te b ound ar y o f th e i n pu t d a ta. i n th e case of th e f i rst figu re, th is o c cu rs after th e ei g h t h b it of th e d a ta b y te h a s b een latch e d in, in d i catin g th at th e in stru ction is b e ing u s ed t o write a si ngle byte. the self-ti m ed write cycle starts, a n d c ontinues for a peri od t w (as specified in ac characteristics ) . at th e end o f th e cycle, th e write in prog ress (wip) b it i s reset t o 0 . if, though, c h i p select ( s ) con tin u e s to b e driv en low, as sh own in th e se co nd figu re, the n e x t b y te o f th e inpu t d a ta is shi f t e d i n , s o t h at m o re t h a n a si n g l e by t e , s t art i ng fr om t h e gi ve n a d dres s t o war d s t h e e n d o f t h e sam e page , ca n be written i n a si ng le in tern al write cycle. each tim e a n e w d a ta b y te is sh ifted in , th e l east sig n i fican t b its of t h e inte rnal a d dress count er a r e in cr eme n te d . i f th e num ber of dat a by t e s se nt t o t h e devi ce e x ce eds t h e page bo und ar y, th e i n ter n al ad dr ess co un ter ro lls ov er to t h e b e g i n n i n g of t h e p a g e , and th e prev i o u s d a ta t h ere are ov er written with th e i n co m i n g d a ta. (th e p a g e size of th ese d e v i ce is 128 bytes) . the i n struction is not acce pted, a n d is no t executed, under the following c o nditions: ? if t h e write enab le latch (wel) b it h a s no t b e en set t o 1 (b y ex ecu ting a write en ab le i n stru ctio n ju st b e fo re) ? if a write cycle is already i n progress ? if t h e device is deselected ? if t h e a d d r esse d page i s i n t h e re gi o n pr ot ect ed by t h e b l oc k p r ot ect (b p 1 and b p 0) bi t s . b y te write ( w rite ) seq u ence (1 by t e ) s w c d q 16-bit address data byte 1 01 2 3 4 5 6 7 0 1 2 3 13 14 15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 0 1 2 3 instruction no te: 1 . th e m e m o ry size is shown in th e add r ess ran g e bits tab l e. r10ds 0 0 46ej 020 0 rev.2.00 page 1 5 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a b y te write (write ) seq u ence (page ) s w c d q 16-bit address data byte 1 01 2 3 4 5 6 7 0 1 2 3 13 14 15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 0 1 2 3 instruction s w c d q data byte 3 data byte n 32 33 34 35 36 37 38 39 7 40 41 42 43 44 45 46 47 high-z v ih v il v ih v il v ih v il 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 data byte 2 no te: 1 . th e m e m o ry size is shown in th e add r ess ran g e bits tab l e. r10ds 0 0 46ej 020 0 rev.2.00 page 1 6 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a data protect the protection feature s of t h e device a r e s u mmarized in t h e fo llowing tab l es. when th e st at us r e gi st er wri t e di sabl e (sr w d) b it o f th e status register is 0 (its initial d e liv ery state), it is po ssi b l e to write to t h e status reg i ster pro v i d e d th at th e write en ab le latch (wel) b it h a s prev i o u s ly b een set b y a write en ab le (wren) in stru ction , reg a rd less whet her w r i t e pr ot ect ( w ) i s dri v en hi gh o r l o w. whe n t h e stat us re gister write disable (sr w d) bit of the stat u s reg i ster is set to 1 , two cases n eed to b e co nsid ered , depe n d i n g on t h e st at e of w r i t e p r ot ect ( w ): ? if w r i t e pr ot ect ( w ) is driv en h i gh , it is po ssi b l e to write to t h e status regi ster provi ded that the write e n able lat c h ( w el ) b i t has pre v i o usl y been set b y a write en ab le (wren) i n structio n . ? if w r i t e pr ot ect ( w ) is driv en l o w, it is n o t possib l e to write to th e status register e v en if t h e write e n abl e latch (w el) b it h a s p r ev iou s ly b e en set b y a writ e en ab le (wr e n) in stru ction . (attem p ts t o write to th e statu s register are re jected, a n d are not acce pt ed for e x ecution). as a conse que nce, all the dat a bytes in the me m o ry area that a r e s o ftware protected (spm ) by t h e b l ock pr ot ect (b p1 , b p 0) bi t s o f t h e st at us r e gi st er, a r e al so har d ware p r ot e c t e d agai nst da t a m odi fi cat i o n . r e gar d l e ss of t h e or der o f t h e t w o e v e n t s , t h e ha rd ware p r ot ect ed m o de (h pm ) ca n be e n t e red: ? by settin g th e statu s reg i ster write disab l e (sr w d) b it after driv ing write pro t ect ( w ) l o w . ? b y dri v i n g w r i t e pr ot ect ( w ) lo w after setting th e statu s reg i ster write disab l e (sr w d) b it. the only way t o e x it the hardware protected mode (hpm ) o n c e en tered is to p u ll write pro t ect ( w ) hig h . if w r i t e pr ot ect ( w ) is pe rm anently tied high, the hardware protected mode (hpm) can never be activated, a n d only the so ft ware p r ot e c t e d m o de (sp m ), usi n g t h e b l ock pr ot ect ( b p1, b p 0 ) bi t s o f t h e st at us r e gi st er, ca n b e use d . write pro t ec ted blo ck size statu s reg i ste r b i ts a r r a y ad d r es s es p r o t ected b p 1 b p 0 pro t ected b l ocks r1ex25512 a 0 0 n o n e n o n e 0 1 u p p e r q u a r t e r c000 h ? ffff h 1 0 u p p e r h a l f 800 0 h ? ffff h 1 1 w h o l e memor y 000 0 h ? ffff h protec tion m odes me mory protec t w s i gna l srwd bit mode write prote c t ion of the statu s reg i ste r pro t ected ar e a * 1 u n p r o t ected area * 1 1 0 0 0 1 1 soft w a r e protected (sp m ) status register is w r itabl e (if the w r en instruction has set the w e l bit). t he values in the bp1 and bp0 b i ts can be chan ged. w r ite protected read y to acc e pt w r ite instructions 0 1 hard w a re protected (hp m ) status register is hard w a r e w r ite protected. t he values i n the bp1 an d bp0 bits cann ot be cha nge d. w r ite protected read y to acc e pt w r ite instructions note: 1. as define d b y t he val ues in th e block protect ed ( bp1, bp0) bits of the status regist er, as sho w n i n the w r ite protected bloc k size table. r10ds 0 0 46ej 020 0 rev.2.00 page 1 7 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a hold condition the hold ( hold ) signal is used t o pause any serial communicatio n s with th e d e v i ce with ou t resettin g t h e clo c k i ng sequ en ce.du r i n g th e ho ld con d ition , t h e serial d a ta ou tpu t (q ) is h i gh im p e d a n c e, an d serial d a ta in pu t (d) and serial clo c k (c) are do n?t care.to enter th e ho ld con d ition , t h e d e v i ce m u st b e selected , with ch i p select ( s ) low . norm all y , th e d e v i ce is k e p t selected , fo r th e wh o l e du ration o f th e ho ld co nd itio n. deselectin g th e d e vice wh ile it is i n th e ho ld cond itio n , h a s th e effect o f resetting th e state o f t h e d e v i ce, an d th i s m ech an is m can b e u s ed if it is requ ired t o reset any proce sses that ha d been in progress . th e ho ld con d i tio n starts wh en th e ho ld ( hold ) signal is drive n low at t h e sam e time as serial clock (c ) alrea d y bei n g lo w (as shown in th e fo llo wi ng figu re).th e ho ld con d ition en ds wh en t h e ho ld ( hol d ) si g n a l is driv en h i gh at th e same tim e as serial clock (c) already being low. th e fo llowing figu re also shows wh at h a pp en s if th e rising an d falling ed ges are no t ti m e d to co i n cid e with serial clo c k (c) bein g l o w . hold condition activ a tio n c hold hold status hold status notes da ta protection at v cc on/off whe n v cc is t u rn ed o n or o ff, no ise on s i n put s ge nerat e d by ext e rnal ci r c ui t s (c pu, etc) m a y act as a trigger a n d turn th e eepr o m t o u n i n t en tion a l prog ram m o d e . to p r ev en t this un in ten tion a l p r og rammin g , th is eeprom h a v e a po wer on reset f u nct i o n . b e care f ul of t h e not i ces descri bed bel o w i n or de r f o r t h e p o w er o n re set fu nct i o n t o ope rat e co rrect l y . vcc s ? s sh ou ld b e f i xed to v cc du r i n g v cc on /o ff. low t o h i gh or h i gh to low tran sitio n du ri n g v cc on/ of f m a y cau se t h e trigger for th e un in t e n tio n a l prog rammin g . ? v cc should be turned on/o ff a f ter the eepr o m is placed i n a standby sta t e. ? v cc shou ld b e tu rn ed on f r o m th e g r ou nd level ( v ss ) in o r d e r for th e eepr o m n o t t o en ter th e un in ten tion a l pr o g ram m i ng m ode. ? v cc tu rn on rate shou ld b e sl ower th an 2 s/v. ? whe n wrsr or w r ite i n structio n is e x ec uted be fo re v cc tu rn s o f f, v cc sh oul d be t u r n ed o f f aft e r w a i t i ng write cycle time (t w ). ? wh en settin g t h e ch ip select sig n a l ( s) to t h e lo w lev e l at po wer on , wait fo r 10 m s o r long er after th e sup p l y vol t a ge 1 . 8 v . 1.8v (vccmin) 10ms min r10ds 0 0 46ej 020 0 rev.2.00 page 1 8 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a packag e dimensions r1ex25 512 asa00 a (p rsp0008 df -b / prev ious co de: fp-8 dbv) prsp0008df-b p-sop8-3.9x4.89-1.27 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.08g 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0 .14 0.254 3.90 0.406 0 .60 0 .889 1.73 reference symbol dimension in millimeters min n om max previous code jeita package code renesas code fp-8dbv 5.15 1 a p 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p * 3 * 2 * 1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e r10ds 0 0 46ej 020 0 rev.2.00 page 1 9 of 20 oct.04, 2010
r1ex25 512 asa00 a /r1ex2551 2ata00 a r1ex25 512 ata0 0a (pts p0008 jc-b / prev ious co de: ttp-8 dav) a l e c 1 b 1 d e a 2 b p c x y h e z l 1 3.00 1.00 0.13 0 8 6.40 0.10 0.15 0.20 0.25 0.03 0.07 0.10 4.40 0.40 0.50 0.60 1.10 reference symbol dimension in millimeters min nom max 3.30 a 1 0.15 0.20 6.60 6.20 0.65 0.10 0.805 * 1 85 e * 2 index mark 14 * 3 p m x y f a d e h z b detail f 1 1 a l l p terminal cross section ( ni/pd/au plating ) c b note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e p-tssop8-4.4x3-0.65 0.034g mass[typ.] ttp-8dav ptsp0008jc-b renesas code jeita package code previous code r10ds 0 0 46ej 020 0 rev.2.00 page 2 0 of 20 oct.04, 2010
all trademarks and re gistere d trademarks ar e t he propert y of their respectiv e o w n e rs. revision histor y r1ex 25512asa00a/ r 1ex25512ata 00a data sheet de s c ription re v . d a t e p a g e s u m m a r y 1.00 jan. 15, 20 10 initial issu e 2.00 oct. 04, 2010 appl y to re nes as electron ics' ne w format an d ne w d o cume nt number. additi on of 8-pi n sop packag e . w h ich prod u c t t y p e no. is r1e x 2 551 2as a 00a. c - 1
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